Soft network-on-chip overlay through a partial reconfiguration region
US11901896B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 24, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Dec 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a programmable logic fabric that has programmable logic circuitry and a partial reconfiguration region. The integrated circuit device also includes a network-on-chip formed in soft logic of the integrated circuit device. Additionally, the network-on-chip is configurable to remain operable during a partial reconfiguration of the partial reconfiguration region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.