Preserving hierarchical structure information within a design file
US11906905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2019 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Nov 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.