Patent · US Active

Memory devices and methods for operating the same

US11907044B2 · kind B2 · utility

0Cited by

1References

21Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Jan Otterstedt · Unterhaching, DE
Wolf Allers · Munich, DE

Key dates

Filing date	Sep 13, 2021
Grant date	Feb 20, 2024
Priority date	—
Expiry date	Sep 13, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/38
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory device comprises a plurality of memory cells and a plurality of evaluation elements, wherein each evaluation element of the plurality of evaluation elements is connectable with a memory cell of the memory device. The memory device further comprises an interconnection unit configured for connecting the plurality of memory cells to a first assignment of evaluation elements in a first state and for connecting the same plurality of memory cells to a second assignment of the evaluation elements in a second state. The memory device comprises an evaluation unit configured for controlling the interconnection unit to transition from the first state to the second state. The evaluation unit is configured for evaluating the plurality of memory cells in the first state to obtain a first evaluation result, and for evaluating the plurality of memory cells in the second state to obtain a second evaluation result.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.