Resistive memory apparatus and operating method thereof and memory cell array thereof
US11908516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Mar 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.