Partial subtractive supervia enabling hyper-scaling
US11908791B2 · kind B2 · utility
1Cited by
10References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 22, 2021 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | May 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an upper section of a supervia formed via subtractive etching and a lower section of the supervia formed via damascene processing. The supervia connects non-adjacent interconnect wiring. The lower section and the upper section of the supervia each define a generally cone-shaped configuration. A distal end of the lower section of the supervia is non-obtuse. Moreover, the lower section of the supervia is formed in a V0 level and the upper section of the supervia is formed in a M1/V1 metallization level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.