Nicholas Anthony Lanzillo
88Patents
4h-index
53Co-inventors
61Inventor score
Filing activity: Jan 23, 2017 → Feb 27, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10319629B1 | Skip via for metal interconnects | Electricity | 12 | Active |
| US10243020B1 | Structures and methods for embedded magnetic random access memory (MRAM) fabrication | Electricity | 11 | Active |
| US9985199B1 | Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield | Electricity | 4 | Active |
| US10256191B2 | Hybrid dielectric scheme for varying liner thickness and manganese concentration | Electricity | 4 | Active |
| US10553789B1 | Fully aligned semiconductor device with a skip-level via | Electricity | 3 | Active |
| US10727124B2 | Structure and method for forming fully-aligned trench with an up-via integration scheme | Electricity | 3 | Active |
| US11195993B2 | Encapsulation topography-assisted self-aligned MRAM top contact | Electricity | 3 | Active |
| US10746782B2 | Accelerated wafer testing using non-destructive and localized stress | Physics | 2 | Active |
| US11152257B2 | Barrier-less prefilled via formation | Electricity | 2 | Active |
| US10770511B2 | Structures and methods for embedded magnetic random access memory (MRAM) fabrication | Electricity | 2 | Active |
| US11276639B2 | Conductive lines with subtractive cuts | Electricity | 2 | Active |
| US11195795B1 | Well-controlled edge-to-edge spacing between adjacent interconnects | Electricity | 2 | Active |
| US11894265B2 | Top via with damascene line and via | Electricity | 1 | Active |
| US11171084B2 | Top via with next level line selective growth | Electricity | 1 | Active |
| US10978343B2 | Interconnect structure having fully aligned vias | Electricity | 1 | Active |
| US11908791B2 | Partial subtractive supervia enabling hyper-scaling | Electricity | 1 | Active |
| US11139201B2 | Top via with hybrid metallization | Electricity | 1 | Active |
| US11189568B2 | Top via interconnect having a line with a reduced bottom dimension | Electricity | 1 | Active |
| US10739397B2 | Accelerated wafer testing using non-destructive and localized stress | Physics | 1 | Active |
| US11756887B2 | Backside floating metal for increased capacitance | Electricity | 1 | Active |
| US9941211B1 | Reducing metallic interconnect resistivity through application of mechanical strain | Electricity | 1 | Active |
| US11195792B2 | Top via stack | Electricity | 1 | Active |
| US10720567B2 | Prevention of switching of spins in magnetic tunnel junctions by on-chip parasitic magnetic shield | Electricity | 1 | Active |
| US11223655B2 | Semiconductor tool matching and manufacturing management in a blockchain | Electricity | 1 | Active |
| US12148682B2 | Memory cell in wafer backside | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.