Array substrate and display panel
US11908804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2019 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Jun 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54486
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an array substrate and a display panel. The array substrate includes a substrate, a first metal layer, a second metal layer, a pixel electrode layer, and an alignment identification terminal that are sequentially stacked. The alignment identification terminal is disposed in at least one of the first metal layer and the second metal layer, and is at least partially disposed in a sub-pixel electrode region. An arrangement of the alignment identification terminal is no longer limited by a narrow frame, and a size can be made larger to meet the needs of a CCD identification, ensuring an accuracy of identification and alignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.