Transmitter circuit and method of operating same
US11914416B2 · kind B2 · utility
0Cited by
12References
12Claims
0Family size
Assignee
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Key dates
| Filing date | May 5, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | May 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transmitter circuit that receives parallel signals and outputs a serial signal in response to the parallel signals may include; a clock generator generating first clock signals having different respective phases, a multiplexer including selection circuits respectively configured to selectively provide at least two of the parallel signals to an output node in response to at least two of the first clock signals, and an output driver generating the serial signal by amplifying a signal at the output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.