Memory device with word line pulse recovery
US11915746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | May 12, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.