Non-volatile memory with isolation latch shared between data latch groups
US11915769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Sep 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a control circuit configured to connect to a bit line that is connected to one or more non-volatile memory cells. The control circuit includes a first plurality of data latches connected to a first local data bus to store first program-verify pass/fail bits and a second plurality of data latches connected to a second local data bus to store second program-verify pass/fail bits for second non-volatile memory cells. The non-volatile memory device further includes a shared isolation latch and one or more interface circuits connected to the first local data bus and the second local data bus. The one or more interface circuits are configured to selectively block the first program-verify pass/fail bits from the first plurality of latches and the second program-verify pass/fail bits from the second plurality of latches according to an indicator bit stored in the shared isolation latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.