Structures and methods of fabricating electronic devices using separation and charge depletion techniques
US11915983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2023 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Jan 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate. Drain electrode contacts are formed over the semiconductor region while gate electrode and source electrode contacts are formed by etching portions of a metallic layer formed over the first …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.