Leo Mathew
64Patents
18h-index
50Co-inventors
87Inventor score
Filing activity: Mar 30, 1998 → Jan 25, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7749884B2 | Method of forming an electronic device using a separation-enhancing species | Emerging Cross-Sectional Technologies | 258 | Active |
| US6686245B1 | Vertical MOSFET with asymmetric gate structure | Electricity | 230 | Expired |
| US7504302B2 | Process of forming a non-volatile memory cell including a capacitor structure | Electricity | 229 | Active |
| US6838322B2 | Method for forming a double-gated semiconductor device | Electricity | 176 | Expired |
| US6831310B1 | Integrated circuit having multiple memory types and method of formation | Electricity | 94 | Expired |
| US5897343A | Method of making a power switching trench MOSFET having aligned source regions | Electricity | 84 | Expired |
| US6921700B2 | Method of forming a transistor having multiple channels | Electricity | 66 | Expired |
| US7013447B2 | Method for converting a planar transistor design to a vertical double gate transistor design | Electricity | 48 | Expired |
| US7265059B2 | Multiple fin formation | Electricity | 42 | Expired |
| US7098502B2 | Transistor having three electrically isolated electrodes and method of formation | Electricity | 41 | Expired |
| US7112832B2 | Transistor having multiple channels | Electricity | 31 | Expired |
| US7585735B2 | Asymmetric spacers and asymmetric source/drain extension layers | Electricity | 30 | Expired |
| US6903967B2 | Memory with charge storage locations and adjacent gate structures | Electricity | 29 | Expired |
| US7018876B2 | Transistor with vertical dielectric structure | Electricity | 26 | Expired |
| US6969656B2 | Method and circuit for multiplying signals with a transistor having more than one independent gate structure | Electricity | 26 | Expired |
| US7709303B2 | Process for forming an electronic device including a fin-type structure | Electricity | 20 | Active |
| US7754560B2 | Integrated circuit using FinFETs and having a static random access memory (SRAM) | Electricity | 19 | Active |
| US6967143B2 | Semiconductor fabrication process with asymmetrical conductive spacers | Emerging Cross-Sectional Technologies | 18 | Expired |
| US7323373B2 | Method of forming a semiconductor device with decreased undercutting of semiconductor material | Electricity | 15 | Expired |
| US6951783B2 | Confined spacers for double gate transistor semiconductor fabrication process | Electricity | 15 | Expired |
| US7192876B2 | Transistor with independent gate structures | Electricity | 15 | Expired |
| US8498140B2 | Two-transistor floating-body dynamic memory cell | Electricity | 13 | Active |
| US7803670B2 | Twisted dual-substrate orientation (DSO) substrates | Electricity | 13 | Active |
| US7432122B2 | Electronic device and a process for forming the electronic device | Emerging Cross-Sectional Technologies | 11 | Active |
| US7452768B2 | Multiple device types including an inverted-T channel transistor and method therefor | Electricity | 11 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.