Semiconductor package
US11916002B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Apr 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.