Device disaggregation for improved performance
US11916076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2020 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Apr 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides chip architectures for FPGAs and other routing implementations that provide for increased memory with high bandwidth, in a reduced size, accessible with reduced latency. Such architectures include a first layer in advanced node and a second layer in legacy node. The first layer includes an active die, active circuitry, and a configurable memory, and the second layer includes a passive die with wiring. The second layer is bonded to the first layer such that the wiring of the second layer interconnects with the active circuitry of the first layer and extends an amount of wiring possible in the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.