Patent · US Active

Burn-in resilient integrated circuit for processors

US11921157B2 · kind B2 · utility

0Cited by

5References

6Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Andreas H. A. Arp · Nufringen, DE
Matthias Ringe · Lörrach, DE
Thomas Makowski · Pfullingen, DE
Michael V. Koch · Ehningen, DE
Fatih Cilek · Eppelheim, DE

Key dates

Filing date	Sep 7, 2021
Grant date	Mar 5, 2024
Priority date	—
Expiry date	Sep 7, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/0015
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.