Peripheral component interconnect express (PCIE) device for supporting separate reference clock(s) operating between host and direct memory access (DMA) controller
US11921657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | May 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.