Stack register having different ferroelectric memory element constructions
US11922055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Sep 1, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.