Memory device having volatile and non-volatile memory cells
US11922984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Sep 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.