Leakage detection for three-dimensional NAND memory
US11923032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2021 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | May 15, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a circuit for detecting leakage between word lines in a memory device. The circuit includes a first and a second coupling capacitor. A first terminals of the first and second coupling capacitors are connected to a first word line and a second word line, respectively. The first terminals of the first and second coupling capacitors are also connected to a first and a second voltage supply, respectively. The circuit further includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupling capacitor and a second input of the comparator is connected to a second terminal of the second coupling capacitor. The comparator is configured to send alarm signal when a differential voltage between the first input and the second input of the comparator is larger than a hysteresis level of the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.