Header circuit placement in memory device
US11923034B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Dec 23, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are related to an integrated circuit including a semiconductor layer. In one aspect, the semiconductor layer includes a first region, a second region, and a third region. The first region may include a circuit array, and the second region may include a set of interface circuits to operate the circuit array. A side of the first region may face a first side of the second region along a first direction. The third region may include a set of header circuits to provide power to the set of interface circuits through metal rails extending along a second direction. A side of the third region may face a second side of the second region along the second direction. In one aspect, the first side extending along the second direction is shorter than the second side extending along the first direction, and the metal rails are shorter than the first side.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.