Halogen treatment for NMOS contact resistance improvement

US11923290B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Siddharth Chouksey · Portland, US
• Gilbert Dewey · Beaverton, US
• Nazila Haratipour · Hillsboro, US
• Mengcheng Lu · Portland, US
• Jitendra Kumar Jha · Hillsboro, US
• Jack T. Kavalieros · Portland, US
• Matthew V. Metz · Portland, US
• Scott B. Clendenning · Portland, US
• Eric Mattson · Portland, US

Key dates

• Filing date: Jun 26, 2020
• Grant date: Mar 5, 2024
• Expiry date: Jul 7, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6219
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.