Semiconductor package including mold layer and manufacturing method thereof
US11923340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2021 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Jan 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.