MOSFET in SiC with self-aligned lateral MOS channel
US11923450B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Aug 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions comprising an access region and a JFET region defining the length of the MOS channel, and wherein the access region and the JFET region are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel is defined by simultaneous creating n-type regions on both sides of the channel using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.