Low-latency time-to-digital converter with reduced quantization step
US11923856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Apr 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.