Patent · US Active

Fast switching of output frequency of a phase locked loop (PLL)

US11923864B2 · kind B2 · utility

0Cited by

27References

14Claims

0Family size

Assignee

Shaoxing Yuanfang Semiconductor Co., Ltd. · CN

Inventors

Srinath Sridharan · Nagamangala, IN
Ankit Seedher · Kanchinakote, IN
Raja Prabhu J · Kanchinakote, IN
Purva Choudhary · Kanchinakote, IN
Sandeep Sasi · Kanchinakote, IN
Akash Gupta · Kanchinakote, IN
Jeevabharathi G · Kanchinakote, IN

Key dates

Filing date	Jun 14, 2022
Grant date	Mar 5, 2024
Priority date	—
Expiry date	Jun 14, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/235
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A phase-locked loop (PLL) is implemented to have another (second) PLL in place of the controlled oscillator. When a known frequency change in the frequency of the output clock is desired, in addition to changing a configuration of the PLL (first PLL), the configuration of the second PLL is also changed to cause the frequency of the output clock to change quickly. In various embodiments, the configuration of the second PLL is changed by changing the divisor of the feedback divider of the second PLL, the divisor in a pre-scaler in the second PLL, the control voltage of a VCO used in the second PLL, and any other point of user control in the second PLL.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.