Vertical semiconductor devices
US11925020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2021 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Dec 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.