System architecture, structure and method for hybrid random access memory in a system-on-chip
US11925035B2 · kind B2 · utility
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Key dates
| Filing date | Oct 26, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Oct 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.