Synchronisation for a multi-tile processing unit
US11928523B2 · kind B2 · utility
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23Claims
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Key dates
| Filing date | Sep 1, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | May 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.