Window program verify to reduce data latch usage in memory device
US11929125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Nov 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.