Mixed pitch track pattern
US11929325B2 · kind B2 · utility
0Cited by
3References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Sep 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Routing layers, e.g., back-end of line (BEOL) routing layers, of a semiconductor device are disclosed. Unlike conventional routing layers, the proposed routing layers include mixed pitch track patterns. As such, routing layers with reduced resistance-capacitance (RC) and low routing cost may be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.