Angelo Pinto
53Patents
14h-index
32Co-inventors
84Inventor score
Filing activity: Apr 24, 1995 → Aug 18, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7199430B2 | Advanced CMOS using super steep retrograde wells | Electricity | 134 | Expired |
| US7064399B2 | Advanced CMOS using super steep retrograde wells | Electricity | 132 | Expired |
| US7655523B2 | Advanced CMOS using super steep retrograde wells | Electricity | 121 | Active |
| US7883977B2 | Advanced CMOS using super steep retrograde wells | Electricity | 121 | Active |
| US7501324B2 | Advanced CMOS using super steep retrograde wells | Electricity | 119 | Expired |
| US8129246B2 | Advanced CMOS using super steep retrograde wells | Electricity | 119 | Active |
| US8247300B2 | Control of dopant diffusion from buried layers in bipolar integrated circuits | Electricity | 97 | Active |
| US6407425B1 | Programmable neuron MOSFET on SOI | Electricity | 75 | Expired |
| US6391707B1 | Method of manufacturing a zero mask high density metal/insulator/metal capacitor | Electricity | 32 | Expired |
| US6667226B2 | Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device | Electricity | 30 | Expired |
| US6646323B2 | Zero mask high density metal/insulator/metal capacitor | Electricity | 23 | Expired |
| US6660616B2 | P-i-n transit time silicon-on-insulator device | Electricity | 21 | Expired |
| US6958523B2 | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits | Electricity | 21 | Expired |
| US6362025B1 | Method of manufacturing a vertical-channel MOSFET | Electricity | 20 | Expired |
| US6770952B2 | Integrated process for high voltage and high performance silicon-on-insulator bipolar devices | Electricity | 14 | Expired |
| US6465830B2 | RF voltage controlled capacitor on thick-film SOI | Electricity | 12 | Expired |
| US6838348B2 | Integrated process for high voltage and high performance silicon-on-insulator bipolar devices | Electricity | 10 | Expired |
| US6284615A | Method and apparatus for the selective doping of semiconductor material by ion implantation | Electricity | 9 | Expired |
| US6794237B2 | Lateral heterojunction bipolar transistor | Electricity | 7 | Expired |
| US7422972B2 | On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits | Electricity | 7 | Expired |
| US6680504B2 | Method for constructing a metal oxide semiconductor field effect transistor | Electricity | 5 | Expired |
| US6894366B2 | Bipolar junction transistor with a counterdoped collector region | Electricity | 5 | Expired |
| US7217322B2 | Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer | Electricity | 4 | Expired |
| US6806159B2 | Method for manufacturing a semiconductor device with sinker contact region | Electricity | 4 | Expired |
| US8138035B2 | Method for forming integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels | Emerging Cross-Sectional Technologies | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.