Passivation layers for semiconductor devices
US11929422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2022 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Jul 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalk of the nanostructured channel regions
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.