Circuits and group III-nitride high-electron mobility transistors with buried p-type layers improving overload recovery and process for implementing the same
US11929428B2 · kind B2 · utility
1Cited by
15References
64Claims
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Key dates
| Filing date | May 17, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Dec 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a recovery enhancement circuit configured to reduce an impact of an overload received by the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.