Fabrication method for JFET with implant isolation
US11929440B2 · kind B2 · utility
1Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2023 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Mar 9, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/106
Abstract
Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.