Stress relief for flip-chip packaged devices
US11930590B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Mar 31, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Jul 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.