Bernardo Gallegos
19Patents
4h-index
21Co-inventors
56Inventor score
Filing activity: Oct 4, 2007 → Dec 19, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7851928B2 | Semiconductor device having substrate with differentially plated copper and selective solder | Electricity | 53 | Active |
| US7939939B1 | Stable gold bump solder connections | Electricity | 26 | Active |
| US9165873B1 | Semiconductor package having etched foil capacitor integrated into leadframe | Electricity | 4 | Active |
| US7808113B2 | Flip chip semiconductor device having workpiece adhesion promoter layer for improved underfill adhesion | Electricity | 4 | Active |
| US9934989B1 | Process for forming leadframe having organic, polymerizable photo-imageable adhesion layer | Electricity | 3 | Active |
| US9054092B2 | Method and apparatus for stopping resin bleed and mold flash on integrated circuit lead finishes | Electricity | 3 | Active |
| US8298874B2 | Packaged electronic devices having die attach regions with selective thin dielectric layer | Electricity | 2 | Active |
| US9373572B2 | Semiconductor package having etched foil capacitor integrated into leadframe | Electricity | 2 | Active |
| US9875930B2 | Method of packaging a circuit | Electricity | 1 | Active |
| US8222748B2 | Packaged electronic devices having die attach regions with selective thin dielectric layer | Electricity | 1 | Active |
| US9142496B1 | Semiconductor package having etched foil capacitor integrated into leadframe | Electricity | 0 | Active |
| US10672692B2 | Leadframe having organic, polymerizable photo-imageable adhesion layer | Electricity | 0 | Active |
| US11930590B2 | Stress relief for flip-chip packaged devices | Electricity | 0 | Active |
| US11848258B2 | Semiconductor package with nickel-silver pre-plated leadframe | Electricity | 0 | Active |
| US12237249B2 | Substrates with solder barriers on leads | Electricity | 0 | Active |
| US12154845B2 | Semiconductor package with nickel-silver pre-plated leadframe | Electricity | 0 | Active |
| US11244881B2 | Package terminal cavities | Electricity | 0 | Active |
| US9536781B2 | Method of making integrated circuit | Electricity | 0 | Active |
| US9142472B2 | Integrated circuit and method of making | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.