Memory error tracking and logging
US11934265B2 · kind B2 · utility
3Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2022 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Jun 4, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.