Inventor · Littleton, MA, US

James Vash

43Patents
5h-index
86Co-inventors
68Inventor score

Filing activity: Sep 28, 2007 → Jun 10, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US8359436B2 Core snoop handling during performance state and power state transitions in a distributed caching agent Physics 16 Active
US8904079B2 Tunneling platform management messages through inter-processor interconnects Physics 9 Active
US11544193B2 Scalable cache coherency protocol Physics 8 Active
US9323316B2 Dynamically controlling interconnect frequency in a processor Emerging Cross-Sectional Technologies 8 Active
US9170946B2 Directory cache supporting non-atomic input/output operations Physics 7 Active
US8250311B2 Satisfying memory ordering requirements between partial reads and non-snoop accesses Physics 5 Active
US8694736B2 Satisfying memory ordering requirements between partial reads and non-snoop accesses Physics 5 Active
US11934265B2 Memory error tracking and logging Physics 3 Active
US10127153B1 Cache dependency handling Physics 3 Active
US8626968B2 Inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline Physics 2 Active
US8868951B2 Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline Emerging Cross-Sectional Technologies 2 Active
US10705960B2 Processors having virtually clustered cores and cache slices Physics 2 Active
US8554851B2 Apparatus, system, and methods for facilitating one-way ordering of messages Physics 1 Active
US9207753B2 Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline Emerging Cross-Sectional Technologies 1 Active
US8756349B2 Inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline Physics 1 Active
US10725919B2 Processors having virtually clustered cores and cache slices Physics 1 Active
US10725920B2 Processors having virtually clustered cores and cache slices Physics 1 Active
US11210104B1 Coprocessor context priority Emerging Cross-Sectional Technologies 1 Active
US11675722B2 Multiple independent on-chip interconnect Emerging Cross-Sectional Technologies 1 Active
US10073779B2 Processors having virtually clustered cores and cache slices Physics 1 Active
US8301907B2 Supporting advanced RAS features in a secured computing system Physics 1 Active
US8769211B2 Monitoring thread synchronization in a distributed cache Physics 0 Active
US10019366B2 Satisfying memory ordering requirements between partial reads and non-snoop accesses Physics 0 Active
US9058271B2 Satisfying memory ordering requirements between partial reads and non-snoop accesses Physics 0 Active
US9703712B2 Satisfying memory ordering requirements between partial reads and non-snoop accesses Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.