Memory command aggregation to improve sequential memory command performance
US11934676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2021 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Nov 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is described, which includes receiving, by a memory subsystem controller from a host system, a host read memory command that references a set of logical block addresses associated with a set of transfer units of a memory device. The controller converts the set of logical block addresses to a set of physical block addresses for the set of transfer units; generates a set of device read memory commands based on the physical block addresses, wherein each device read memory command references at least one physical block address; and generates a first aggregated device read memory command based on a first device read memory command and a second read memory command in response to determining that the first device read memory command is associated with the second device read memory command. The controller thereafter transmits the first aggregated device read memory command to the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.