Data reordering at a memory subsystem
US11934686B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2022 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Apr 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A set of host data items is received for programming to the memory subsystem. The set of host data items is programmed to a first region of the memory subsystem that includes one or more memory devices. A determination is made that a sequence at which the set of host data items are programmed across memory devices of the first region does not correspond to a target sequence associated with accessing the set of host data items via the first region. The target sequence corresponds to a sequence that enables a host data items programmed to the memory sub-system to be accessed in parallel. The set of host data items is copied from the first region to a second region of the memory subsystem. A sequence at which the set of host data items is copied to memory devices of the second region corresponds to the target sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.