Error aware module redundancy for machine learning
US11934932B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2020 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Jan 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples herein propose operating redundant ML models which have been trained using a boosting technique that considers hardware faults. The embodiments herein describe performing an evaluation process where the performance of a first ML model is measured in the presence of a hardware fault. The errors introduced by the hardware fault can then be used to train a second ML model. In one embodiment, a second evaluation process is performed where the combined performance of both the first and second trained ML models is measured in the presence of a hardware fault. The resulting errors can then be used when training a third ML model. In this manner, the three trained ML models are trained to be error aware. As a result, during operation, if a hardware fault occurs, the three ML models have better performance relative to three ML models that where not trained to be error aware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.