Data compression support for accelerated processor
US11935153B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 28, 2020 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Dec 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/423
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Data processing methods and devices are provided. A processing device comprises memory and a processor. The memory, which comprises a cache, is configured to store portions of data. The processor is configured to issue a store instruction to store one of the portions of data, provide identifying information associated with the one portion of data, compress the one portion of data; and store the compressed one portion of data across multiple lines of the cache using the identifying information. In an example, the one portion of data is a block of pixels and pixels and the processor is configured to request pixel data for a pixel of a compressed block of pixels, send additional requests for data for other pixels determined to belong to the compressed pixel block and provide an indication that the requests are for pixel data belonging to the compressed block of pixels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.