Bit line sensing circuit comprising a sample and hold circuit
US11935601B2 · kind B2 · utility
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10References
11Claims
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Key dates
| Filing date | Aug 14, 2020 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Aug 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memories, memory controllers, and computing systems and their methods of operation are disclosed. In some embodiments, a method of accessing a memory includes accessing a first bit line corresponding to a sense amplifier and accessing a second bit line corresponding to the sense amplifier. In some embodiments, a memory controller includes a second memory configured to store data of a second data type. In some embodiments, a method includes operating a memory in a second mode in response to receiving an input to change the operation of the memory from a first mode to the second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.