Page buffer circuits of three-dimensional memory device
US11935619B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 4, 2022 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Apr 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.