Patent · US Active

Chip warpage reduction via raised free bending and re-entrant (auxetic) trace geometries

US11935810B2 · kind B2 · utility

0Cited by

0References

8Claims

0Family size

Assignee

Board of Trustees of the University of Arkansas · US

Inventors

David Huitink · Prairie Grove, US
John Harris · Kenagh, IE

Key dates

Filing date	May 6, 2021
Grant date	Mar 19, 2024
Priority date	—
Expiry date	Oct 9, 2041

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY10T428/24942
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A microelectronic device and method of making the same including a substrate and at least one expansion layer that adds stress to the substrate when said substrate expands.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.