Semiconductor package manufacturing method, and adhesive sheet used therein
US11935865B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2019 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Sep 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for producing a semiconductor package, capable of effectively suppressing contamination of a chemical liquid and unintended peeling-off of a reinforcing sheet, is provided. This method includes providing a tacky sheet including a substrate sheet, and a soluble tacky layer and a banking tacky layer on at least one surface of the substrate sheet; making a first laminate including a redistribution layer; using the tacky sheet to obtain a second laminate having a second support substrate bonded to a surface on the redistribution layer side of the first laminate with the tacky layer therebetween; peeling off the first support substrate, pretreating the resulting third laminate; mounting a semiconductor chip on a pretreated surface of the redistribution layer; immersing the third laminate in a solution to dissolve or soften the tacky layer; and peeling off the second support substrate in a state where the tacky layer is dissolved or softened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.