Semiconductor structure forming method and semiconductor structure
US11935917B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2021 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Jan 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/30
Abstract
A method of forming a semiconductor structure includes: a substrate is provided, the substrate at least comprising a conducting layer; a bottom supporting layer and a stacking structure being formed on a top surface of the substrate, the stacking structure including a sacrificial layer and a supporting portion that are sequentially stacked and formed; the stacking structure and the bottom supporting layer are partially etched to expose the conducting layer to form a through hole; the supporting portion of a partial width exposed from a sidewall of the through hole is laterally etched to form an air gap; a protective layer filling the air gap is formed; a lower electrode electrically connected with the conducting layer is formed on the sidewall of the through hole and a sidewall of the protective layer; the sacrificial layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.