Chen Wu
11Patents
3h-index
3Co-inventors
42Inventor score
Filing activity: Apr 23, 2019 → Jul 30, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11004773B2 | Porous barrier layer for improving reliability of through-substrate via structures and methods of forming the same | Electricity | 7 | Active |
| US11037908B2 | Bonded die assembly containing partially filled through-substrate via structures and methods for making the same | Electricity | 5 | Active |
| US11094653B2 | Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same | Electricity | 4 | Active |
| US11362079B2 | Bonded die assembly containing a manganese-containing oxide bonding layer and methods for making the same | Electricity | 3 | Active |
| US11088116B2 | Bonded assembly containing horizontal and vertical bonding interfaces and methods of forming the same | Electricity | 2 | Active |
| US11276705B2 | Embedded bonded assembly and method for making the same | Electricity | 0 | Active |
| US11929255B2 | Method of high-density pattern forming | Electricity | 0 | Active |
| US11270963B2 | Bonding pads including interfacial electromigration barrier layers and methods of making the same | Electricity | 0 | Active |
| US11935917B2 | Semiconductor structure forming method and semiconductor structure | Electricity | 0 | Active |
| US11239204B2 | Bonded assembly containing laterally bonded bonding pads and methods of forming the same | Electricity | 0 | Active |
| US11430745B2 | Semiconductor die containing silicon nitride stress compensating regions and method for making the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.