Transistor having asymmetric threshold voltage and buck converter
US11936299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2020 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Oct 5, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/158
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.