Patent · US Active

Dual chip clock synchronization

US11940836B2 · kind B2 · utility

0Cited by

23References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Hagen Schmidt · Lörrach, DE
Andreas H. A. Arp · Nufringen, DE
Daniel Kiss · Stuttgart, DE

Key dates

Filing date	Mar 31, 2022
Grant date	Mar 26, 2024
Priority date	—
Expiry date	Oct 4, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Clocks of two semiconductor circuit are set to a common clock source when both the first and second semiconductor circuits are in a slow clock speed at which an input/output (IO) at an interface between the first and second semiconductor circuit is capable of operating. Division counters of the two clocks are synchronized at the slow clock speed. The two semiconductor circuits are switched to a fast clock speed that is a multiple of the slow speed, wherein the IO is not capable of operating at the fast clock speed. Pulses from a division counter of the first circuit are sent to a spare division counter of the second circuit, and then a primary division counter of the second counter is aligned to this spare division counter to keep the two circuits synchronized at the fast clock speed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.